Wille84
27.05.2006, 16:07
Tossa ois perus tiukat latenssit jos joku tarvii "250fsb:lle"
Cpu fsb:250
Ldt/Dsb frequency ratio: 4
Cpu/Fsb frequency ratio: 11
Pci-e frequency:100mhz
Cpu vid startup: 1.450v
Cpu vid control:1.30
Cpu vid special control: above vid 112%
Ldt voltage: 1.30v
chipset v:vakiot "toistaiseksi"
Dram voltage: 2.7v "ei tarvi enempää"
Timings:
Dram frequency set: 200=ram/fsb:01/01
Command per clock (cpc): 1T eli enable
Cas latency control (tcl): 3 "kokeilin 2.5 mutta ei toiminu"
Ras to Cas delay (trcd): 3 bus clocks
Min ras active time (tras): 8 bus clocks "itsellä 7"
Row precharge time (trp): 2 bus clocks
Row cycle time (trc): 07 clocks
Row refresh cyc time(trfc): 14 bus clocks
Row to row delay (trrd) : 02 bus clocks
Write recovery time (twr) : 02 bus clocks
Write to read delay (twtr) : 02 bus clocks
Read to write delay (trwt) : 02 bus clocks "jos ei toimi nii 03"
Refresh period (THEF) : auto
Odd divisor correct : DISABLE <--- !!!
Dram bank interleave : enable
Dqs skew control : auto
Dqs skew value : 0
Dram drive strenght: 4
Dram data drive strenght : reduce 00%
Max async latency : 0.8 nano seconds
Dram response time : fast "normal jos ei toimi"
Read preamble time : 0.5 nano seconds
Idle cycle limit : 16 cycles
Dynamic counter : DISABLE
R/W queue bypass : 16x
Bypass max : 07x
32 byte granularity : disable(4bursts)
Cpu fsb:250
Ldt/Dsb frequency ratio: 4
Cpu/Fsb frequency ratio: 11
Pci-e frequency:100mhz
Cpu vid startup: 1.450v
Cpu vid control:1.30
Cpu vid special control: above vid 112%
Ldt voltage: 1.30v
chipset v:vakiot "toistaiseksi"
Dram voltage: 2.7v "ei tarvi enempää"
Timings:
Dram frequency set: 200=ram/fsb:01/01
Command per clock (cpc): 1T eli enable
Cas latency control (tcl): 3 "kokeilin 2.5 mutta ei toiminu"
Ras to Cas delay (trcd): 3 bus clocks
Min ras active time (tras): 8 bus clocks "itsellä 7"
Row precharge time (trp): 2 bus clocks
Row cycle time (trc): 07 clocks
Row refresh cyc time(trfc): 14 bus clocks
Row to row delay (trrd) : 02 bus clocks
Write recovery time (twr) : 02 bus clocks
Write to read delay (twtr) : 02 bus clocks
Read to write delay (trwt) : 02 bus clocks "jos ei toimi nii 03"
Refresh period (THEF) : auto
Odd divisor correct : DISABLE <--- !!!
Dram bank interleave : enable
Dqs skew control : auto
Dqs skew value : 0
Dram drive strenght: 4
Dram data drive strenght : reduce 00%
Max async latency : 0.8 nano seconds
Dram response time : fast "normal jos ei toimi"
Read preamble time : 0.5 nano seconds
Idle cycle limit : 16 cycles
Dynamic counter : DISABLE
R/W queue bypass : 16x
Bypass max : 07x
32 byte granularity : disable(4bursts)